Embodiments of the inventive concept relate to methods of managing dynamic memory reallocation. More particularly, certain embodiments of the inventive concept relate to methods of dynamically managing addresses corresponding to memory regions of a wide input/output (I/O) mobile dynamic random access memory (DRAM). Certain other embodiments of the inventive concept relate to methods of dynamically managing addresses corresponding to memory regions of a main memory. Still other embodiments of the inventive concept relate to devices capable of performing such methods.
The term “cache memory” is typically applied to high-speed memories designed operate in close conjunction with one or more processor(s) or similar computational component(s). Cache memory is commonly implemented using random access memory (RAM) that allows relatively fast data access. In contrast, the term “main memory” is typically applied to bulk storage memories that operate a relatively lower speeds.
When a read request directed to “read data” is received in a system, a processor may first determine whether the requested read data is stored in a cache memory. If the read data is identified in a cache memory, the processor need not access the main memory. However, if the read data is not found in a cache memory, the processor must then access the main memory to retrieve it.
Cache memories may be used in a variety of configurations. Consistent with hierarchal system definitions, a cache memory may be classified as a level-1 (L1) cache, a level-2 (L2) cache, and a level-3 (L3) cache, and so on. Generally speaking, a L1 cache is commonly integrated on a chip with one or more corresponding processor(s) to form a so-called “processor core” or “processor multi-core”. In contrast, a L2 cache is typically disposed outside the processor core but may be integrated within a System on Chip (SoC) as a physically separate chip. In still further contrast, a L3 cache is typically disposed outside the SoC (e.g.,) on a motherboard. With this disposition, the L3 cache may serve as a buffer memory between the processor(s) and the main memory.
Memory space is a scarce commodity in computational systems. Memory space may be scarce as a function of time (i.e., temporally crowded or bottlenecked) or it may be scarce as a function of overall data storage demand. In either event, memory space must be effectively managed to ensure proper operation of a host device incorporating or accessing the memory. One approach to the effective management of memory space is referred to as “dynamic memory allocation.” Dynamic memory allocation methods seek to efficiently allocate space in a main memory to the current requirements of one or more processor(s) reading data from and/or writing data (collectively or singularly “accessing data”) to the main memory. As memory systems become expansive, and as computational systems become more complicated the need to effectively perform dynamic memory allocation increases.